Design and Simulation of the Digital Controller Block of a Neural Stimulation Chip for a Brain Implant

Fahimi Hanzaee, Farnaz; Ahmadi, Mohammad Mehdi

doi:10.22041/ijbme.2018.90981.1386

Authors

¹ M.Sc, Department of Biomedical Engineering, Amirkabir University of Technology, Tehran, Iran

² Assistant Professor, Department of Biomedical Engineering, Amirkabir University of Technology, Tehran, Iran

https://doi.org/10.22041/ijbme.2018.90981.1386

Abstract

Nowadays, implantable electrical neural stimulation is extensively used to treat or alleviate certain brain-related health conditions, such as in deep brain stimulation (DBS) or in vagus nerve stimulation (VNS). In this paper, we present a digital controller block, designed for a neuroelectrical stimulator chip dedicated for a brain implant.The presented design is very power and area-efficient and provides a great flexibibity in programming the specifications of the stimulation pulses. The duration of each stimulation pulse can programmed to be from 4 µs to 4 ms, and the amplitude of each pulse could be from 4 µA to 1 mA. The stimulation pulses could be either monophasic or biphasic, In addition, in biphasic stimulation, the priority of the cathodic pulse over the anodic pulse, or vice versa, could be pragrammed. The interphase delay between the anodic and cathodic phases could be programmed to be between 4 µs and 512 µs. The controller controls 16 stimulation sites, four of which can be stimulated simoultaneualy. The 16 stimulation sites are divided into four groups, each of which is stimulated by a current-controlled stimulation circuit. Each stimulation circuit is controlled by a local digital controller (LDC), which receives its data from a global digital controller (GDC). The designed controller blocks have been implemented and tested on a Spartan-6 field-programmable gate array (FPGA) board, before being implemented as an application-specific integrated circuit (ASIC) layout. The ASIC circuit has been designed using 0.18-µm CMOS technology. Based on the layout, each LDC occupies an area of 19,160 µm² and consumes 12 µW of power from a 1.8V supply. On the other hand, the GDC takes up an area of 4,246 µm² and consumes 8.2 µW of power. We have also created a graphical user interface (GUI) to be able to program the stinulation chip.

Keywords

Main Subjects

Medical Instrumentation

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Iranian Journal of Biomedical Engineering

Design and Simulation of the Digital Controller Block of a Neural Stimulation Chip for a Brain Implant

References

References

Volume 12, Issue 2
September 2018
Pages 147-159

Design and Simulation of the Digital Controller Block of a Neural Stimulation Chip for a Brain Implant

References

References

Volume 12, Issue 2September 2018Pages 147-159

Volume 12, Issue 2
September 2018
Pages 147-159